Microchip Technology /ATSAMV71Q19B /SysTick /CSR

Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text

Interpret as CSR

31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (VALUE_0)ENABLE 0 (VALUE_0)TICKINT 0 (VALUE_0)CLKSOURCE 0 (COUNTFLAG)COUNTFLAG

ENABLE=VALUE_0, CLKSOURCE=VALUE_0, TICKINT=VALUE_0

Description

Control and Status Register

Fields

ENABLE

Enables the counter

0 (VALUE_0): counter disabled

1 (VALUE_1): counter enabled

TICKINT

Enables SysTick exception request

0 (VALUE_0): counting down to 0 does not assert the SysTick exception request

1 (VALUE_1): counting down to 0 asserts the SysTick exception request

CLKSOURCE

Indicates the clock source

0 (VALUE_0): external clock

1 (VALUE_1): processor clock

COUNTFLAG

Returns 1 if timer counted to 0 since last time this was read

Links

()